1. Field of the Invention
The present invention relates to a semiconductor device such as DRAMs and a method of manufacturing the same.
2. Description of the Background Art
FIG. 217 is a circuit diagram illustrating a construction of a memory cell of a DRAM. As shown in FIG. 217, a capacitor C1 and an NMOS transistor Q1 are disposed between terminals P1 and P2. One electrode (a cell plate electrode) of the capacitor C1 is connected to the terminal P1, and the other electrode (a storage node electrode) is connected to one electrode (a source or drain electrode) of the NMOS transistor Q1. The gate of the NMOS transistor Q1 is connected to a terminal P3, and the back gate is connected to a terminal P4. In general, the terminal P1 is provided with a fixed potential, the terminal P2 is connected to a bit line, the terminal P3 is connected to a word line, and the terminal P4 serves as a terminal for setting the potential of a well region where the NMOS transistor Q1 is to be formed. Followings are examples of a memory cell element having a construction of xe2x80x9c1 Tr (transistor)+1 capa (capacitor)xe2x80x9d shown in FIG. 217.
FIG. 218 is a plan view illustrating a planar structure of a stack-type memory cell (Type 1). FIG. 219 is a sectional view taken along the line A1xe2x80x94A1 in FIG. 218.
Referring to these figures, an NMOS transistor Q1 and a capacitor C1 are formed within a P well region 22 in which elements are isolated by an isolation insulating film 23. The P well region 22 is selectively formed at an upper layer portion of a semiconductor substrate 21, as shown in FIG. 220. With a plurality of isolation insulating films 23, the P well region 22 is isolated transistor by transistor.
As shown in FIGS. 218 and 219, source/drain regions 31 and 32 are selectively formed in the surface of the P well region 22. A gate oxide films 33 and a gate electrode 34 are formed between the source/drain regions 31 and 32, and a sidewall 35 is formed on both side surfaces of the gate oxide film 33 and a gate electrode 34. The NMOS transistor Q1 is made up of the source/drain regions 31 and 32, gate oxide film 33, gate electrode 34 and sidewall 35.
A storage node electrode 41-1 is formed on the source/drain region 31 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-1 is formed on the upper and side surfaces of the storage node electrode 41-1, and a cell plate electrode 43-1 is formed on the upper and side surfaces of the insulating film 42-1. The capacitor C1 is made of up the storage node electrode 41-1, insulating film 42-1 and cell plate electrode 43-1.
The storage node electrode 41-1 is of a plate structure having a square shape in plan configuration.
FIG. 221 is a plan view illustrating a planar structure of a stack-type memory cell (Type 2). FIG. 222 is a sectional view taken along the line A2xe2x80x94A2 in FIG. 221.
Referring to these figures, a storage node electrode 41-2 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-2 is formed on the upper and side surfaces of the storage node electrode 41-2, and a cell plate electrode 43-2 is formed on the upper and side surfaces of the insulating film 42-2. A capacitor C1 is made up of the storage node electrode 41-2, insulating film 42-2 and cell plate electrode 43-2.
The storage node electrode 41-1 is of a cylindrical structure having a circular shape in plan configuration. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 223 is a plan view illustrating a planar structure of a stack-type memory cell (Type 3). FIG. 224 is a sectional view taken along the line A3xe2x80x94A3 in FIG. 223.
Referring to these figures, a storage node electrode 41-3 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-3 is formed on the upper and inner surfaces of the storage node electrode 41-3, and a cell plate electrode 43-3 is formed on the upper and inner surfaces of the insulating film 42-3. A capacitor C1 is made up of the storage node electrode 41-3, insulating film 42-3 and cell plate electrode 43-3.
The storage node electrode 41-3 has a hollow cylindrical structure having a circular shape in plan configuration, and the insulating film 42-3 and cell plate electrode 43-3 are formed within this cylindrical structure. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 225 is a plan view illustrating a planar structure of a stack-type memory cell (Type 4). FIG. 226 is a sectional view taken along the line A4xe2x80x94A4 in FIG. 225.
Referring to these figures, a storage node electrode 41-4 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-4 is formed so as to cover the convexoconcave part of the storage node electrode 41-4, and a cell plate electrode 43-4 is formed so as to cover the insulating film 42-4. A capacitor C1 is made up of the storage node electrode 41-4, insulating film 42-4 and cell plate electrode 43-4.
The storage node electrode 41-4 has a fin structure made up of a convex part having a large square shape in plan configuration and a concave part having a small area in plan configuration. This allows for a more junction capacitance. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 227 is a sectional view illustrating a sectional structure of a trench-type memory cell (Type 1). As shown in the figure, a cell plate electrode 43-5 of trench structure is buried within a P well region 22. The cell plate electrode 43-5 is covered at its surroundings with an insulating film 42-5, and a source/drain region 63 is formed so as to cover the surroundings of the insulating film 42-5.
The source/drain region 63 functions as one electrode of the NMOS transistor Q1 and also functions as a storage node electrode of the capacitor C1. Otherwise, the construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 228 is a sectional view illustrating a sectional structure of a trench-type memory cell (Type 2). As shown in the figure, a cell plate electrode 43-6 of trench structure is buried within a P well region 22. An insulating film 42-6 is formed so as to cover the side surface of the cell plate electrode 43-6, and a source/drain region 64 is formed so as to cover part of the surroundings of the insulating film 42-6.
The gate electrode 67 is partially buried in the P well region 22 and is isolated from the cell plate electrode 43-6 with an insulating region 70 interposed therebetween. A gate oxide film 66 is formed on one side surface of the gate electrode 67, and the side surface end of the gate electrode 67 overlaps in part the end of the source/drain region 64 via the gate oxide film 66.
A sidewall 68 is disposed above the P well region 22 via the gate oxide film 66 and is adjacent to the gate electrode 67. A source/drain region 65 is formed adjacent to the underside of the sidewall 68 in the P well region 22.
Thus, an NMOS transistor Q1 is made up of the source/drain regions 64 and 65, gate oxide film 66, gate electrode 67 and sidewall 68, and a capacitor C1 is made up of the source/drain region 64, insulating film 42-5 and insulating film 42-6. That is, the source/drain region 64 functions as one electrode of the NMOS transistor Q1 and also functions as a storage node electrode of the capacitor C1.
FIG. 229 is a plan view illustrating a planar structure of a stack-type memory cell (Type 5). FIG. 230 is a sectional view taken along the line A5xe2x80x94A5 in FIG. 229.
Referring to these figures, a storage node electrode 41-7 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-7 is formed on the upper and side surfaces of the storage node electrode 41-7, and a cell plate electrode 43-7 is formed on the upper and side surfaces of the insulating film 42-7. A capacitor C1 is made up of the storage node electrode 41-7, insulating film 42-7 and cell plate electrode 43-7.
The storage node electrode 41-7 is of a cylindrical structure having a circular shape in plan configuration and it has rough upper and side surfaces. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 231 is a plan view illustrating a planar structure of a stack-type memory cell (Type 6). FIG. 232 is a sectional view taken along the line A6xe2x80x94A6 in FIG. 231.
Referring to these figures, a storage node electrode 41-8 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-8 is formed on the upper surface and inner side surface of the storage node electrode 41-8, and a cell plate electrode 43-8 is formed on the upper surface and inner side surface of the insulating film 42-8. A capacitor C1 is made up of the storage node electrode 41-8, insulating film 42-8 and cell plate electrode 43-8.
The storage node electrode 41-8 is of a hollow cylindrical structure having a circular shape in plan configuration and it has rough upper and side surfaces. The insulating film 42-8 and cell plate electrode 43-8 are disposed in this hollow cylinder. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 233 is a plan view illustrating a planar structure of a stack-type memory cell (Type 7). FIG. 234 is a sectional view taken along the line A7xe2x80x94A7 in FIG. 233.
Referring to these figures, a storage node electrode 41-9 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 44-9 is formed on the upper and side surfaces of the storage node electrode 41-9, and a cell plate electrode 43-9 is formed on the upper and inner surfaces of the insulating film 44-9. A capacitor C1 is made up of the storage node electrode 41-9, insulating film 44-9 and cell plate electrode 43-9.
The insulating film 44-9 is formed from a material having a relatively high relative dielectric constant k. Examples of materials having a high relative dielectric constant are SiON, Si3N4, Al2O3, ZrO2, HfO2, Ta2O5, La2O3, TiO2, and BASrTiO3 (BST).
The storage node electrode 41-9 is of a cylindrical structure having a circular shape in plan configuration. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 235 is a plan view illustrating a planar structure of a stack-type memory cell (Type 8). FIG. 236 is a sectional view taken along the line A8xe2x80x94A8 in FIG. 235.
Referring to these figures, a storage node electrode 41-10 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 44-10 is formed on the upper surface and inner side surface of the storage node electrode 41-10, and a cell plate electrode 43-10 is formed on the upper surface and inner side surface of the insulating film 44-10. A capacitor C1 is made up of the storage node electrode 41-10, insulating film 44-10 and cell plate electrode 43-10.
Like the insulating film 44-9, the insulating film 44-10 is formed from a material having a relatively high relative dielectric constant k. The storage node electrode 41-10 is of a hollow cylindrical structure having a circular shape in plan configuration. The storage node electrode 44-10 and cell plate electrode 43-10 are formed within this hollow cylinder. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 237 is a sectional view illustrating a sectional structure of a trench-type memory cell (Type 3). As shown in the figure, an insulating film 44-11 is disposed between a cell plate electrode 43-11 and source/drain region 63. Like the insulating films 44-9 and 44-10, the insulating film 44-11 is formed from a material having a relatively high relative dielectric constant k. Otherwise, the construction of this memory cell is the same as that shown in FIG. 106, and a description thereof is thus omitted.
FIG. 238 is a sectional view illustrating a sectional structure of a trench-type memory cell (Type 4). As shown in the figure, an insulating film 44-12 is disposed between a cell plate electrode 43-12 and source/drain region 64. Like the insulating films 44-9 to 44-11, the insulating film 44-12 is formed from a material having a relatively high relative dielectric constant k. Otherwise, the construction of this memory cell is the same as that shown in FIG. 106, and a description thereof is thus omitted.
FIG. 239 is a plan view illustrating a planar structure of a stack-type memory cell (Type 9). FIG. 240 is a sectional view taken along the line A9xe2x80x94A9 in FIG. 239. As shown in these figures, an insulating film 44-13 is disposed between a storage node electrode 41-13 and cell plate electrode 43-13. Like the insulating films 44-9 to 44-12, the insulating film 44-13 is formed from a material having a relatively high relative dielectric constant k. Otherwise, the construction of this memory cell is the same as that shown in FIGS. 229 and 230, and a description thereof is thus omitted.
FIG. 241 is a plan view illustrating a planar structure of a stack-type memory cell (Type 10). FIG. 242 is a sectional view taken along the line A10xe2x80x94A10 in FIG. 241. As shown in these figures, an insulating film 44-14 is disposed between a storage node electrode 41-14 and cell plate electrode 43-14. Like the insulating films 44-9 to 44-13, the insulating film 44-14 is formed from a material having a relatively high relative dielectric constant k. Otherwise, the construction of this memory cell is the same as that shown in FIGS. 231 and 232, and a description thereof is thus omitted.
FIGS. 243 to 251 are sectional views illustrating a method of manufacturing a memory cell element of xe2x80x9c1 Tr+1 capa type.xe2x80x9d Referring to these figures, a method of manufacturing a memory cell element having a memory capacitor with a plate structure that is the basis for stack-type ones (see FIGS. 218 and 219) will be described hereinafter with emphasis on the capacitor making process.
Referring to FIG. 243, the elements on a semiconductor substrate are isolated by an isolation insulating film 23, and boron ions are implanted (due to diffusion) at an energy of 300 keV and a dose of 1xc3x971013/cm2, thereby to form a P well region 22. Then, boron ions are successively implanted at an energy of 120 keV and a dose of 5xc3x971012/cm2, then at an energy of 30 keV and a dose of 5xc3x971012/cm2, thereby to form a channel region (not shown).
Referring to FIG. 244, a gate oxide film 33 composed of a silicon oxide film is formed in a thickness of 3 to 10 nm, and a gate electrode 34 of dual structure made up of a polysilicon layer and a tungsten silicon layer, each having a thickness of 50 nm, is then formed on the gate oxide film 33. By using the gate electrode 34 as a mask, phosphorus ions are implanted at an energy of 30 keV and a dose of 1xc3x971014/cm2. Further, a sidewall 35 composed of a silicon oxide film having a width of 5 to 15 nm is formed on the both side surfaces of the gate electrode 34. By using the gate electrode 34 and sidewall 35 as a mask, arsenic ions are implanted at an energy of 10 keV and a dose of 1xc3x971014/cm2, thereby to obtain source/drain regions 31 and 32.
This results in an NMOS transistor Q1 comprising the source/drain regions 31, 32, gate oxide film 33, gate electrode 34 and sidewall 35.
Referring to FIG. 245, an interlayer insulating film 24 is deposited on the entire surface, and a patterned resist 25 is then formed on the interlayer insulating film 24. By using the resist 25 as a mask, the interlayer insulating film 24 is selectively etched away, thereby to obtain a contact hole 40 having a diameter of 0.2 xcexcm and extending through the interlayer insulating film 24.
Referring to FIG. 246, the resist 25 is removed and a (doped) polysilicon layer 45 is then deposited in a thickness of 500 nm on the entire surface.
Referring to FIG. 247, by using a patterned resist 26 as a mask, the polysilicon layer 45 is etched away to obtain a storage node electrode 41. The resist 26 is then removed as shown in FIG. 248.
Referring to FIG. 249, an insulating film 46 and a polysilicn layer 47 are successively formed on the entire surface. For instance, the insulating film 46 may be of a dual structure which comprises SiO2 having a thickness of 7.5 nm and Si3N4 having a thickness of 7.5 nm. Alternatively, it may be TaO5 having a thickness of 15 nm, or BST having a thickness of 15 nm. The polysilicon layer 47 is formed in a thickness of 200 nm.
Referring to FIG. 250, a patterned resist 27 is formed on the polysilicon layer 47.
Referring to FIG. 251, by using the resist 27 as a mask, the insulating film 46 and polysilicon layer 47 are selectively removed to obtain an insulating film 42 and a cell plate electrode 43, and the resist 27 is then removed. This results in a memory cell element having plate type memory capacitors (41 to 43).
Various parameters that determine operating characteristics of an NMOS transistor Q1 used in a memory cell element are determined in well-balance taking mutual tradeoff into consideration. Tradeoff factors to be discussed here are (i) relaxation of gate edge field, (ii) suppression of threshold voltage rise, (iii) assurance of resistance to punch-through, and (iv) leak current reduction (relaxation of junction capacitance).
FIG. 252 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD (lightly doped drain) structure. As shown in the figure, LDD regions 31b and 32b having a low impurity concentration are disposed at an edge proximate region of a gate electrode 34 in source/drain regions 31 and 32. The source/drain regions 31 and 32 are formed by the LDD regions 31b and 32b, together with source/drain primary regions 31a and 32a. 
This LDD structure can exhibit the best effect on relaxation of gate edge field, whereas it is less effective on suppression of threshold voltage rise and on leak current reduction, and it acts negatively on assurance of resistance to punch-through.
FIG. 253 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD (double doped drain) structure. As shown in the figure, a source/drain region 31 (32) is made up of a high concentration region 31c (32c) and a low concentration region 31d (32d) that are formed by double diffusion. The high concentration region 31c is formed at a relatively shallow region except for a gate edge proximate region, and the low concentration region 31d is formed at a relatively deep region of the gate edge proximate region and at relatively deep region except for the gate edge proximate region.
This DDD structure exhibits the best effect on relaxation of gate edge field and provides a relatively good result on leak current reduction, whereas it is less effective on suppression of threshold voltage rise and acts negatively on assurance of resistance to punch-through, similarly to the LDD structure.
Thus, the usual LDD structure and DDD structure suffer from the disadvantage that these are unsuitable for assurance of resistance to punch-through.
FIG. 254 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD structure employing a channel dope region. As shown in the figure, in addition to the LDD structure, a P type channel dope region 38 is disposed so as to overlap in part a lower layer of a source/drain primary region 31a (32a) and overlap the lowermost part of an LDD region 31b (32b).
The LDD structure employing the channel dope region exhibits the best effect on assurance of resistance to punch-through and exhibits a relatively good effect on relaxation of gate edge field, whereas it acts negatively on suppression of threshold voltage rise and on leak current reduction.
FIG. 255 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD structure employing a channel dope region. As shown in the figure, in addition to the DDD structure, a P type channel dope region 39 is disposed so as to overlap in part a low concentration region 31d (32d).
The DDD structure employing the channel dope region exhibits the best effect on assurance of resistance to punch-through and exhibits a relatively good effect on relaxation of gate edge field, whereas it acts negatively on suppression of threshold voltage rise and on leak current reduction.
Thus, the LDD structure and DDD structure, each employing the channel dope region, suffer from the disadvantage that these structures are unsuitable for leak current reduction and suppression of threshold voltage rise.
FIG. 256 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD structure employing a local channel dope region. As shown in the figure, in addition to the LDD structure, a P type local channel dope region 48 is disposed under a gate electrode 34, without overlapping source/drain regions 31 and 32.
The LDD structure employing the local channel dope region exhibits a relatively good effect on assurance of resistance to punch-through and relaxation of gate edge field, and it can be arranged such that this structure does not act negatively on leak current reduction, but acts negatively on suppression of threshold voltage rise.
FIG. 257 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD structure employing a local channel dope region. As shown in the figure, in addition to the DDD structure, a P type local channel dope region 49 is disposed under a gate electrode 34 in little or no overlap relationship with source/drain regions 31 and 32.
The DDD structure employing the local channel dope region exhibits a relatively good effect on assurance of resistance to punch-through, relaxation of gate edge field, and leak current reduction, whereas it acts negatively on suppression of threshold voltage rise.
Thus, the LDD structure and DDD structure, each employing the local channel dope region, suffer from the disadvantage that these are unsuitable for suppression of threshold voltage rise.
FIG. 258 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD structure employing a pocket region. As shown in the figure, in addition to the LDD structure, P type pocket regions 51 and 52 are disposed which respectively overlap source/drain regions 31, 32 and extend to a lower region of the source/drain regions 31, 32 and to a channel region in a P well region 22.
The LDD structure employing the pocket region exhibits the best effect on suppression of threshold voltage rise and exhibits a relatively good effect on assurance of resistance to punch-through and on relaxation of gate edge field, whereas it acts negatively on leak current reduction.
FIG. 259 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD structure employing a pocket region. As shown in the figure, in addition to the DDD structure, P type pocket regions 56 and 57 are disposed which respectively overlap source/drain regions 31, 32 and extend to a lower region of the source/drain regions 31, 32 and to a channel region in a P well region 22.
The DDD structure employing the pocket region exhibits the best effect on suppression of threshold voltage rise and exhibits a relatively good effect on assurance of resistance to punch-through and on relaxation of gate edge field, whereas it acts negatively on leak current reduction.
Thus, the LDD structure and DDD structure, each employing the pocket region, suffer from the disadvantage that these structures are unsuitable for leak current reduction.
FIG. 260 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD structure employing a shallow pocket region. As shown in the figure, in addition to the LDD structure, P type shallow pocket regions 53 and 54 are disposed which respectively overlap mostly of source/drain regions 31 and 32, extend slightly to a channel region in a P well region 22, and have approximately the same forming depth as the source/drain regions 31 and 32.
The LDD structure employing the shallow pocket region exhibits a relatively good effect on suppression of threshold voltage rise, assurance of resistance to punch-through, and relaxation of gate edge field, and further, it does not act negatively on leak current reduction.
FIG. 261 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD structure employing a shallow pocket region. As shown in the figure, in addition to the DDD structure, P type shallow pocket regions 58 and 59 are disposed which respectively overlap mostly of source/drain regions 31 and 32, extend slightly to a channel region in a P well region 22, and have a slightly shallower forming depth than the source/drain regions 31 and 32.
The DDD structure employing the shallow pocket region exhibits a relatively good effect on suppression of threshold voltage rise, assurance of resistance to punch-through, and relaxation of gate edge field, and further, it does not act negatively on leak current reduction.
Thus, the LDD structure and DDD structure, each employing the shallow pocket region, suffer from the disadvantage that these fail to exhibit the best characteristic in all the tradeoff factors.
In memory cell elements of DRAMs etc., when less leak current is desired only in a source/drain region to be connected to a storage node electrode of a memory capacitor, it can be considered to increase the forming depth of the source/drain region on the storage node side, as shown in FIGS. 262 and 263.
In the case of FIG. 262, a source/drain region 31 is made up of partial source/drain regions 31e and 31f, and the forming depth of the partial source/drain region 31f is increased.
In the case of FIG. 263, a source/drain region 31 (32) is made up of partial source/drain regions 31e (32e) and 31g (32g), and the forming depth of the partial source/drain region 31g is increased.
Thus, the source/drain regions 31f and 31g having the increased forming depth enables to improve the characteristic about leak current reduction.
If assurance of resistance to punch-through is satisfied, it is unnecessary to form the source/drain regions in the same fashion as with FIG. 263. That is, the partial source/drain region 31g having the increased forming depth may be formed only in the source/drain region 31 on the storage node side as shown in FIG. 262.
FIGS. 264 to 268 are sectional views illustrating a sequence of steps in a method of manufacturing a memory cell element in which the forming depth of a source/drain region on the storage node side is increased. The method will be described hereinafter by referring to these figures.
Referring to FIG. 264, after the elements on a semiconductor substrate are isolated by an isolation insulating film 23, a P well region 22 is formed in the same manner as the step in FIG. 243, and a channel region (not shown) is then formed.
Referring to FIG. 265, in the same manner as the step shown in FIG. 244, there is obtained an NMOS transistor Q1 comprising a source/drain partial region 31e, source/drain region 32, gate oxide film 33, gate electrode 34 and sidewall 35.
Referring to FIG. 266, in the same manner as the step shown in FIG. 245, an interlayer insulating film 24 is deposited on the entire surface, thereby obtaining a contact hole 40 extending through the interlayer insulating film 24.
Referring to FIG. 267, an N type impurity ions 49 such as of phosphorus is implanted from the contact hole 40, thereby to form a source/drain partial region 31f. 
Referring to FIG. 268, a storage node electrode 41 is obtained in the same manner as shown in the steps in FIGS. 246 to 248.
Further, the steps shown in FIGS. 249 to 251 are performed to complete a memory cell element shown in FIG. 263.
As described above, the MOS transistor of the LDD structure or DDD structure employing the shallow pocket region enables to obtain such characteristics as not to cause any negative actions on relaxation of gate edge field, suppression of threshold voltage rise, assurance of resistance to punch-through, and leak voltage reduction (relaxation of junction capacitance).
On the other hand, MOS transistors used in memory cells of DRAMs call for the following characteristics:
i) relatively good characteristic about relaxation of gate edge field;
ii) characteristic in such degree as to cause no negative action about suppression of threshold voltage rise;
iii) the best characteristic about assurance of resistance to punch-through; and
iv) the best characteristic about leak current reduction.
There has been a problem in that the mentioned characteristics cannot be realized by employing any of the channel dope region, local channel dope region, pocket region and shallow pocket region in MOS transistor structures such as the LDD structure and DDD structure.
According to a first aspect of the invention, a semiconductor device comprises: a transistor forming region of a first conductivity type disposed in a semiconductor substrate; first and second source/drain regions of a second conductivity type disposed selectively in the surface of the transistor forming region, the transistor forming region between the first and second source/drain regions being defined as a channel region; a gate insulating film disposed on the channel region; a gate electrode disposed on the gate insulating film; and a transistor characteristic adjusting region of the first conductivity type disposed in the transistor forming region so as to at least overlap in part the channel region, wherein an insulating gate type transistor is defined by the first and second source/drain regions, the channel region, the gate insulating film, the gate electrode and the transistor characteristic adjusting region, and the first conductivity type impurity concentration of the transistor characteristic adjusting region and the second conductivity type impurity concentration of the first and second source/drain regions are set so as to satisfy the following conditions: 1018xe2x89xa6C1xe2x89xa61019/cm3 . . . (I); and C2/10xe2x89xa6C1xe2x89xa6C2 . . . (II) where C1 is the maximum value of the first conductivity type impurity concentration of the transistor characteristic adjusting region except for a surface proximate region of the transistor forming region, and C2 is the maximum value of the second conductivity type impurity concentration of the first and second source/drain regions except for the surface proximate region.
According to a second aspect of the invention, the semiconductor device of the first aspect is characterized in that the transistor characteristic adjusting region includes a channel dope region disposed at a predetermined depth from the surface of the transistor forming region so as to overlap the channel region in a plane view over substantially the entire surface of the channel region.
According to a third aspect of the invention, the semiconductor device of the second aspect is characterized in that the channel dope region includes a normal channel dope region extending over substantially the entire surface of the transistor forming region in a plane view.
According to a fourth aspect of the invention, the semiconductor device of the second aspect is characterized in that the channel dope region includes a local channel dope region disposed in little or no overlap relationship with the first and second source/drain regions.
According to a fifth aspect of the invention, the semiconductor device of the first aspect is characterized in that the transistor characteristic adjusting region includes first and second pocket regions overlapping substantially the whole of the first and second source/drain regions and extending from the first and second source/drain regions to part of the channel region.
According to a sixth aspect of the invention, the semiconductor device of the fifth aspect is characterized in that the first and second pocket regions include first and second normal pocket regions extending also to the underside of the first and second source/drain regions.
According to a seventh aspect of the invention, the semiconductor device of the fifth aspect is characterized in that the first and second pocket regions include first and second shallow pocket regions having approximately the same forming depth as the first and second source/drain regions.
According to an eighth aspect of the invention, the semiconductor device of the first aspect is characterized in that the transistor characteristic adjusting region includes: a first partial transistor characteristic adjusting region disposed at a predetermined depth in the transistor forming region; and a second partial transistor characteristic adjusting region disposed in the transistor forming region so as to be deeper than the first partial transistor characteristic adjusting region.
According to a ninth aspect of the invention, the semiconductor device of the first aspect is characterized in that the transistor characteristic adjusting region includes: a first channel dope region overlapping the channel region in a plane view over substantially the entire surface of the channel region; a second channel dope region disposed at a region deeper than the first channel dope region so as to overlap the channel region in a plane view over substantially the entire surface of the channel region; and first and second pocket regions overlapping substantially the whole of the first and second source/drain regions and extending from the first and second source/drain regions to the channel region.
According to a tenth aspect of the invention, the semiconductor device of the first aspect is characterized in that the first and second source/drain regions have in their surfaces first and second high impurity concentration regions, respectively, having a higher impurity concentration than other regions, the first and second high impurity concentration regions being spaced a predetermined distance away from the channel region.
According to an eleventh aspect of the invention, the semiconductor device of the first aspect further comprises a capacitor provided with one electrode electrically connected to one of the first and second source/drain regions.
According to a twelfth aspect of the invention, a method of manufacturing a semiconductor device comprises the steps of: (a) providing a semiconductor substrate having a transistor forming region of a first conductivity type; (b) forming a gate insulating film and a gate electrode on a channel region in the transistor forming region; (c) selectively introducing impurity of a second conductivity type into the transistor forming region, to form first and second source/drain regions of the second conductivity type sandwiching the channel region and being adjacent to the channel region; and (d) introducing impurity of the first conductivity type into the transistor forming region to form a transistor characteristic adjusting region of the first conductivity type so as to at least overlap in part the channel region, wherein an insulating gate type transistor is defined by the first and second source/drain regions, the channel region, the gate insulating film, the gate electrode and the transistor characteristic adjusting region, and the first conductivity type impurity concentration of the transistor characteristic adjusting region and the second conductivity type impurity concentration of the first and second source/drain regions are set so as to satisfy the following conditions: 1018xe2x89xa6C1xe2x89xa61019/cm3 . . . (I); and C2/10xe2x89xa6C1xe2x89xa6C2 . . . (II), where C1 is the maximum value of the first conductivity type impurity concentration of the transistor characteristic adjusting region except for a surface proximate region of the transistor forming region, and C2 is the maximum value of the second conductivity type impurity concentration of the first and second source/drain regions except for the surface proximate region.
According to a thirteenth aspect of the invention, the method of the twelfth aspect is characterized in that the step (d) includes the step of forming a channel dope region as the transistor characteristic adjusting region overlapping the channel region in a plane view over substantially the entire surface of the channel region, at a predetermined depth from the surface of the transistor forming region.
According to a fourteenth aspect of the invention, the method of the thirteenth aspect is characterized in that: the channel dope region includes a normal channel dope region formed over substantially the entire surface of the transistor forming region in a plane view; and the step (d) includes the step of introducing impurity of the first conductivity type into the entire surface of the transistor forming region.
According to a fifteenth aspect of the invention, the method of the thirteenth aspect is characterized in that: the channel dope region includes a local channel dope region formed in little or no overlap relationship with the first and second source/drain regions; and the step (d) includes the step of selectively introducing impurity of the first conductivity type into the channel region in the transistor forming region.
According to a sixteenth aspect of the invention, the method of the twelfth aspect is characterized in that: the transistor characteristic adjusting region includes first and second pocket regions overlapping substantially the whole of the first and second source/drain regions and extending from the first and second source/drain regions to the channel region; and the step (d) includes the step, after the step (b), of forming the first and second pocket regions by introducing impurity of the first conductivity type into the transistor forming region by using the gate electrode as a mask.
According to a seventeenth aspect of the invention, the method of the sixteenth aspect is characterized in that: the first and second pocket regions include first and second normal pocket regions extending also to the underside of the first and second source/drain regions; the step (c) includes a process of implanting ions of the second conductivity type at a first energy by using the gate electrode as a mask; and the step (d) includes a process of implanting ions of the first conductivity type at a second energy higher than the first energy by using the gate electrode as a mask.
According to an eighteenth aspect of the invention, the method of the sixteenth aspect is characterized in that: the first and second pocket regions include first and second shallow pocket regions having approximately the same forming depth as the first and second source/drain regions; and the process of introducing impurity of the first conductivity type in said step (d) includes a process of obliquely implanting impurity ions of the first conductivity type.
According to a nineteenth aspect of the invention, the method of the twelfth aspect is characterized in that: the transistor characteristic adjusting region includes a first partial transistor characteristic adjusting region formed at a predetermined depth in the transistor forming region and a second partial transistor characteristic adjusting region formed at a depth deeper than the first partial transistor characteristic adjusting region in the transistor forming region; the step (d) includes the steps of (d-1) implanting impurity ions of the first conductivity type to form the first partial transistor characteristic adjusting region, and (d-2) implanting impurity ions of the first conductivity type to form the second partial transistor characteristic adjusting region; and that ion implantation conditions of the steps (d-1) and (d-2) is set so that the second partial transistor characteristic adjusting region is deeper than the first partial transistor characteristic adjusting region.
According to a twentieth aspect of the invention, the method of the twelfth aspect is characterized in that: the transistor characteristic adjusting region includes a first channel dope region overlapping substantially the entire surface of the channel region in a plane view, a second channel dope region formed at a region deeper than the first channel dope region so as to overlap substantially the entire surface of the channel region in a plane view, and first and second pocket regions overlapping substantially the whole of the first and second source/drain regions and extending from the first and second source/drain regions to the channel region; and that the step (d) includes the steps of: (d-1) implanting impurity ions of the first conductivity type to form the first channel dope region; (d-2) implanting impurity ions of the first conductivity type to form the second channel dope region; and (d-3) implanting, after the step (b), impurity ions of the first conductivity type by using the gate electrode as a mask, to form the first and second pocket regions.
According to a twenty-first aspect of the invention, the method of the twelfth aspect is characterized in that: the first and second source/drain regions have in their surfaces first and second high impurity concentration regions, respectively, having a higher impurity concentration than other regions, each of first and second high impurity concentration regions being spaced a predetermined distance away from the channel region; that the step (c) includes the steps of: (c-1) implanting, after the step (b), impurity ions of the first conductivity type by using the gate electrode as a mask, to form the first and second source/drain regions of the first conductivity type; and (c-2) implanting, after the step (c-1), impurity ion of the first conductivity type by using the gate electrode as a mask, to form the first and second high impurity concentration regions in the surface of the first and second source/drain regions; and that ion implantation conditions of the step (c-2) is set so that the first and second high impurity concentration regions are spaced the predetermined distance away from the channel region.
According to a twenty-second aspect of the invention, the method of the twelfth aspect is characterized in that: the first and second source/drain regions have in their surfaces first and second high impurity concentration regions, respectively, having a higher impurity concentration than other regions, each of first and second high impurity concentration regions being spaced a predetermined distance away from the channel region, the method further comprising the step of: (e) forming a sidewall on both side surfaces of the gate electrode, wherein the step (c) includes the steps of: (c-1) implanting, after the step (b) and before the step (e), impurity ions of the first conductivity type by using the gate electrode as a mask, to form the first and second source/drain regions of the first conductivity type; and (c-2) implanting, after the step (e), impurity ions of the first conductivity type by using the gate electrode and the sidewall as a mask, to form the first and second high impurity concentration regions of the first conductivity type.
According to a twenty-third aspect of the invention, the method of the twelfth aspect is characterized in that: at least one of the first and second source/drain regions has in its surface a high impurity concentration region having a higher impurity concentration than other regions, the high impurity concentration region being spaced a predetermined distance away from the channel region, the method further comprising the step of: (f) forming, after the step (c), a mask layer on the entire surface, the mask layer having an opening above part of at least one of the first and second source/drain regions, wherein the step (c) includes the steps of: (c-1) implanting, after the step (b) and before the step (f), impurity ions of the first conductivity type by using the gate electrode as a mask, to form the source/drain regions; and (c-2) implanting, after the step (f), impurity ions of the first conductivity type from the opening of the mask layer, to form the high impurity concentration region in a region including the surface of the source/drain regions.
According to a twenty-fourth aspect of the invention, the method of the twenty-third aspect further comprises the steps of: (g) filling, after the step (c-1), the opening with an impurity diffusion source of the second conductivity type; and (h) diffusing a second impurity from the impurity diffusion source into the surface of the high impurity concentration region, to form an impurity diffusion region.
According to a twenty-fifth aspect of the invention, the method of the twelfth aspect further comprises the step of (i) electrically connecting one electrode to one of the first and second source/drain regions to form a capacitor.
The insulating gate type transistor of a semiconductor device in the first aspect satisfies the conditions (I) and (II), so that the depletion layer also extends into the first and second source/drain regions at the time of operation. This provides a good characteristic about assurance of resistance to punch-through and a reduction in leak current from the bottom of the first and second source/drain regions.
In the semiconductor device of the second aspect, the above-mentioned good characteristics can be obtained by forming, as a transistor characteristic adjusting region, a channel dope region overlapping mostly of the channel region having a strong relationship with the characteristic of the insulating gate type transistor.
In the semiconductor device of the third aspect, the formation of the normal channel dope region is relatively easy because it is formed over the entire surface of the transistor forming region.
In the semiconductor device of the fourth aspect, the formation of the local channel dope region provides a better characteristic about leak current reduction.
In the semiconductor device of the fifth aspect, an increase in threshold voltage can be suppressed effectively by forming the first and second pocket regions to be partially formed only in the channel region, as a transistor characteristic adjusting region.
In the semiconductor device of the sixth aspect, the normal pocket region is formed so as to extend to a lower part than the first and second source/drain regions. Thereby, the normal pocket region can easily extend to part of the channel region.
In the semiconductor device of the seventh aspect, the shallow pocket region has approximately the same forming depth as the first and second source/drain regions. This permits a further effect of reducing leak current from the bottom of the first and second source/drain regions.
In the semiconductor device of the eighth aspect, a better characteristic about assurance of resistance to punch-through and about reduction in leak current from the bottom of the first and second source/drain regions can be obtained by individually setting the impurity concentration of the first and second partial transistor characteristic adjusting regions.
In the semiconductor device of the ninth aspect, a better characteristic about threshold voltage control, assurance of resistance to punch-through and a reduction in leak current from the bottom of the first and second source/drain regions, can be obtained by individually setting the impurity concentration of the first and second channel dope regions and that of the first and second pocket regions.
In the semiconductor device of the tenth aspect, the presence of the first and second high impurity concentration regions allows for a reduction in the resistance value of the current path on the surface of the transistor forming region, without adversely affecting assurance of resistance to punch-through and leak current reduction.
In the semiconductor device of the eleventh aspect, it is able to provide a memory cell comprising an insulating gate type transistor having a good characteristic about assurance of resistance to punch-through and leak current reduction, and a capacitor for storage.
In the insulating gate type transistor obtained by the method of manufacturing a semiconductor device in the twelfth aspect, the conditions (I) and (II) are satisfied so that a depletion layer also extends into the first and second source/drain regions at the time of operation. It is therefore able to obtain a good characteristic about assurance of resistance to punch-through and about a reduction in leak current from the bottom of the first and second source/drain regions.
In the insulating gate type transistor obtained by the method of manufacturing a semiconductor device in the thirteenth aspect, the above-mentioned good characteristic can be obtained by forming, as a transistor characteristic adjusting region, the channel dope region of which flat region overlaps mostly of the channel region having a strong relationship with the characteristic of the insulating gate type transistor.
With the method of the fourteenth aspect, it is relatively easy to form the normal channel dope region by introducing the first impurity into the entire surface of the transistor forming region in the step (d).
In the insulating gate type transistor obtained by the method of the fifteenth aspect, a better characteristic about leak current reduction can be obtained by providing the local channel dope region.
In the insulating gate type transistor obtained by the method of the sixteenth aspect, an increase in threshold voltage can be suppressed effectively by forming the first and second pocket regions disposed only in part of the channel region, as a transistor characteristic adjusting region.
In the method of the seventeenth aspect, the first and second normal pocket regions extending to part of the channel region can be formed relatively with ease by the step (d) in which the first conductivity type ions are implanted at the second energy higher than the first energy by using the gate electrode as a mask.
In the method of the eighteenth aspect, the shallow pocket region of the insulating gate type transistor has approximately the same forming depth as the first and second source/drain regions. This permits a further effect of reducing leak current from the bottom of the first and second source/drain regions.
In the method of the nineteenth aspect, the insulating gate type transistor having a better characteristic about assurance of resistance to punch-through and about a reduction in leak current from the bottom of the first and second source/drain regions, can be obtained by the steps (d-1) and (d-2) of individually setting the impurity concentration of the first and second partial transistor characteristic adjusting regions.
In the method of the twentieth aspect, the insulating gate type transistor having a better characteristic about threshold voltage control, assurance of resistance to punch-through, and a reduction in leak current from the bottom of the first and second source/drain regions, can be obtained by the steps (d-1), (d-2) and (d-3) in which the impurity concentration of the first and second channel dope regions and that of the first and second pocket regions are set individually.
In the insulating gate type transistor of the twenty-first aspect, the presence of the first and second high impurity concentration regions allows for a reduction in the resistance value of the current path on the surface of the transistor forming region, without adversely affecting assurance of resistance to punch-through and leak current reduction.
With the method of the twenty-second aspect, the step (c-2) is performed by providing an offset corresponding to the thickness from the channel region to the sidewall. This permits a precise formation of the first and second high impurity concentration regions spaced a predetermined distance from the channel region, respectively.
With the method of the twenty-third aspect, the step (c-2) is performed by providing an offset corresponding to the distance from the channel region to the opening. This permits a precise formation of the high impurity concentration region spaced a predetermined distance from the channel region.
With the method of the twenty-fourth aspect, it is relatively easy to obtain the source/drain regions of triple diffusion structure by the step (h) in which the impurity diffusion region is formed by allowing the second impurity to diffuse from the impurity diffusion source into the surface of the high impurity concentration region.
The method of the twenty-fifth aspect can provide a memory cell comprising the insulating gate type transistor having a good characteristic about assurance of resistance to punch-through and leak current reduction, and a capacitor for storage.
It is an object of the present invention to overcome the aforementioned problems by providing a semiconductor device having a MOS transistor capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and about leak current reduction, as well as a method of manufacturing the same.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.